机译:SoC中基于内核的嵌入式混合信号模块测试
NXP Semicond., Netherlands;
IEEE standards; design for testability; embedded systems; integrated circuit design; integrated circuit testing; mixed analogue-digital integrated circuits; radiofrequency integrated circuits; system-on-chip; DFT architecture; IEEE test standard; RF module; SoC; core-based design; core-based testing; embedded mixed-signal module; industrial product; test development approach; computer-aided test; core-based test; mixed-signal test;
机译:一种用于测试基于嵌入式内核的SOC的新型可重构包装器及其关联的调度算法
机译:同时进行基于温度核的SOC测试的测试计划和TAM总线分配
机译:基于内核的SoC的晶圆级减少引脚数测试的测试长度和TAM优化
机译:混合信号SoC测试:是否正在进行混合信号的测试设计?
机译:集成模拟电路和模块的混合信号测试。
机译:VHL框和SOCS框域确定泛素连接酶的Cul2-Rbx1和Cul5-Rbx2模块的结合特异性
机译:嵌入式基于内核的SoC的通用资源分配和测试计划方案