Silicon-Proven Timing Signoff Methodology Using Hazard-Free Robust Path Delay Tests

摘要

Ensuring a tight correlation between pre-silicon static timing analysis (STA) and post-silicon timing analysis is essential to a robust design flow. Researchers from Intel describe a novel methodology to validate path level STA on silicon using standard scan architecture and path delay tests that are generated by commercial EDA tools. -Vivek Chickermane, Cadence Design Systems