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Robust Delay Fault Testing Using Effective Signal Integrity-Aware Pattern Generation Methodologies.

机译:使用有效的信号完整性感知模式生成方法进行鲁棒的延迟故障测试。

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摘要

The semiconductor industry has widely accepted transition delay fault (TDF) and path delay fault (PDF) testing as techniques to structurally detect gross timing defects in modern integrated circuits (ICs). As effective as delay fault testing is for detecting such defects, as process technology continues to reach the ultra-deep sub-micron scale, interconnect parasitic effects have been playing a more integral role. However, these effects are context sensitive and will impact chip performance only under certain states. Current automatic test pattern generation (ATPG) tools are not aware of the context of the patterns and the performance impact that these at-speed test patterns will have on the chip during test. As a result, test escapes may occur since paths can be activated functionally that create excessive noise and critical failures in the field while it had already passed at-speed manufacturing tests. In this work, we propose novel techniques to generate patterns that are signal integrity-aware. By considering the locality of switching activity during pattern generation, both IR-drop and crosstalk can be leveraged to change the chip performance during test. Including these enhancements during pattern generation will produce more robust pattern sets that will increase defect coverage, assist in first silicon validation and debug, and improve device reliability in the field. In addition, a new model for estimating the switching activity during ATPG is presented to avoid the time consuming process of logic simulation and can be used to improve the performance of the proposed signal integrity-aware pattern generation. Also, a technique to avoid functionally untestable states is presented to maintain behavior during test that is closer to functional. This can be utilized in conjunction with the proposed pattern generation methodologies to prevent overtesting while still reaching the functional limits of the design.
机译:半导体行业已广泛接受过渡延迟故障(TDF)和路径延迟故障(PDF)测试,以此作为在结构上检测现代集成电路(IC)中总体时序缺陷的技术。随着延迟故障测试对于检测此类缺陷的有效性,随着制程技术继续达到超深亚微米规模,互连寄生效应起着越来越重要的作用。但是,这些影响是上下文相关的,仅在某些状态下才会影响芯片性能。当前的自动测试模式生成(ATPG)工具尚不了解模式的上下文以及这些高速测试模式在测试过程中对芯片的性能影响。结果,可能会发生测试逃逸,因为在功能已通过高速制造测试的情况下,路径可以在功能上激活,从而在现场产生过多的噪声和严重故障。在这项工作中,我们提出了新颖的技术来生成信号完整性感知的模式。通过考虑图案生成期间开关活动的局部性,可以利用IR压降和串扰来改变测试期间的芯片性能。在图案生成过程中包括这些增强功能将产生更健壮的图案集,这些图案集将增加缺陷覆盖率,协助进行首次硅片验证和调试并提高现场设备的可靠性。此外,提出了一种用于估计ATPG期间的开关活动的新模型,以避免逻辑仿真的耗时过程,并可用于改善建议的信号完整性感知模式生成的性能。另外,提出了一种避免功能不可测试状态的技术,以在测试过程中保持更接近功能的行为。可以与建议的模式生成方法结合使用,以防止过度测试,同时仍能达到设计的功能极限。

著录项

  • 作者

    Lee, Jeremy.;

  • 作者单位

    University of Connecticut.;

  • 授予单位 University of Connecticut.;
  • 学科 Engineering Computer.
  • 学位 Ph.D.
  • 年度 2011
  • 页码 139 p.
  • 总页数 139
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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