A hardware counter-based toolkit for the analysis of memory accesses in SMPs

摘要

In this paper, a set of three hardware counter (HC)-based tools to characterise memory access of parallelrncodes in Symmetric Multiprocessors (SMPs) is presented. This toolkit simplifies accessing and programmingrnHCs, which are included in modern microprocessors. Hardware counters are used to obtain informationrnabout memory accesses in a parallel code at very low cost. This information is presented to the user in arnfriendly way. The first tool can be used to automatically monitor the memory accesses of a system and tornanalyse a code even if the source is not available. The second tool allows the user to insert in a source code,rnin a simple and transparent way, the instructions needed to monitor and manage HCs. This way, specific partsrnof the code can be analysed. The user can either add appropriate directives to a C code or use a graphicalrninterface to select those parts of the code to be analysed. The tool takes this source file and automaticallyrnadds the monitoring code. The third tool takes the information gathered by the aforementioned tools, processesrnit and displays it graphically. This tool shows the information in a comprehensive and simple way,rnallowing the user to adjust the level of detail. The aim of these tools was to characterise the memory accessesrnof parallel codes in multicore systems, in which the cache hierarchy can greatly influence the performance.rnFor illustrative purposes, these tools were used to carry out two case studies, a sparse matrix vector productrnand a dot product. These studies have been made in two different environments. Anyway, they can be usedrnin almost any system as long as the necessary HCs are available.