Design Constraints for the Memory Systems of Useful SMPs

摘要

In recent years, many vendors have produced cache coherent shared memory symmetric multiprocessors. While most of the systems that used, at most, eight processors have been successes, the same statement cannot be made for the larger, more scalable systems. Some of the larger systems have been extremely successful, others have been marginally to reasonably successful, and a few have been outright failures. Based on the author's experience programming the KSR1, Convex Exemplar, Silicon Graphics Inc. (SGI) Challenge and Power Challenge, and the SGI Origin 2000, some insights into key design issues for a successful cache coherent shared memory symmetric multiprocessor are discussed. The report concludes with a frequently overlooked issue; the cost effectiveness of some of these designs. In particular, any design that requires the widespread replication of key data structures will have a hard time establishing its cost effectiveness (even if it does meet the requirements for performance and scalability).