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A radix-4 modular multiplication hardware algorithm for modular exponentiation

机译:用于模幂运算的radix-4模块化乘法硬件算法

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A fast radix-4 modular multiplication hardware algorithm is proposed. It is efficient for modular exponentiation with a large modulus, used in public-key cryptosystems such as the RSA cryptosystem. The operands and the result of multiplication which are intermediate results in modular exponentiation are represented in a redundant representation. The computation proceeds in serial-parallel fashion. Each subtraction for the division for residue calculation is embedded in the repeated multiply-add. Each intermediate result is represented in a more redundant representation than that for the operands and the result, so that the number of the required addition/subtractions is reduced. All addition/subtraction are carried out without carry propagation. A serial-parallel modular multiplier based on the algorithm has a regular cellular array structure with a bit slice feature and is suitable for VLSI implementation.
机译:提出了一种快速的radix-4模块化乘法硬件算法。它对于使用大模量的模幂运算非常有效,可用于RSA密码系统等公钥密码系统。在模幂运算中处于中间结果的操作数和乘法结果以冗余表示形式表示。计算以串行-并行方式进行。用于残差计算的除法的每个减法都嵌入重复的乘法加法中。每个中间结果都以比操作数和结果更多的冗余表示来表示,因此减少了所需的加/减数。所有加/减操作均不进行进位传播。基于该算法的串并行模乘器具有规则的蜂窝阵列结构,具有位片特征,适合于VLSI实现。

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