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Reliable floating-point arithmetic algorithms for error-coded operands

机译:可靠的浮点算术算法,用于错误编码的操作数

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Reliable floating-point arithmetic is vital for dependable computing systems. It is also important for future high-density VLSI realizations that are vulnerable to soft-errors. However, the direct checking of floating-point arithmetic is still an open problem. The author presents a set of reliable floating-point arithmetic algorithms for low-cost residue encoded and Berger encoded operands, respectively. Closed form equations are derived for floating-point addition, subtraction, multiplication, and division. Given the standard IEEE floating-point numbers, the proposed reliable floating-point multiplication algorithms for low-cost residue encoded operands are extremely low-cost: it requires less than 8% of hardware redundancy in all cases. For reliable floating-point addition and subtraction, the author finds the hardware redundancy ratios of applying low-cost residue code is about the same as that of applying Berger code: less than 40% of hardware redundancy for single precision numbers and about 16% for double precision numbers. For reliable floating-point division, Berger encoded operands yields hardware cost-effectiveness: about 45% for single precision numbers and about 36% for double precision numbers.
机译:可靠的浮点算法对于可靠的计算系统至关重要。对于将来容易受到软错误影响的高密度VLSI实现而言,这一点也很重要。但是,直接检查浮点算术仍然是一个未解决的问题。作者分别针对低成本的残差编码和Berger编码的操作数提供了一套可靠的浮点算法。为浮点加法,减法,乘法和除法导出了闭式方程。在给定标准IEEE浮点数的情况下,针对低成本残差编码操作数提出的可靠浮点乘法算法的成本极低:在所有情况下,其所需硬件冗余都不到8%。对于可靠的浮点加法和减法,作者发现应用低成本残码的硬件冗余率与应用Berger码的硬件冗余率大致相同:对于单精度数字,硬件冗余的比例不到40%,对于单精度数字,硬件冗余的比例约为16%。双精度数字。对于可靠的浮点除法,Berger编码的操作数可产生硬件成本效益:单精度数字约为45%,双精度数字约为36%。

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