Block-Precise Processors: Low-Power Processors with Reduced Operand Store Accesses and Result Broadcasts

摘要

Power is a first order design constraint for most processors today. Benefits of low power designs include lower manufacturing and operating costs and a longer battery life. In this work we propose an out of order processor architecture called Block-precise processor (B-Processor) that is designed for low power consumption. The B-Processor consumes lower power than typical processor designs by eliding the write of results of many instructions to the reorder buffer and to the register file, which are power hungry structures. The B-Processor reduces power consumption even further by omitting the broadcast of certain results over multiple levels of the bypass network. Experimental results show that on average the B-Processor spends 15.1 percent less power on register file and reorder buffer accesses and 14.5 percent less power on broadcasting results. In combination with register file caching, on average the B-Processor saves 28.7 percent power for accessing the register file and the reorder buffer.