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A platform for the automatic generation of attribute evaluation hardware systems

机译:自动生成属性评估硬件系统的平台

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Attribute grammars (AG) allow the addition of context-sensitive properties into context free grammars, augmenting their expressional capabilities by using syntactic and semantic notations, making them in this way a really useful tool for a considerable number of applications. AGs have extensively been utilized in applications such as artificial intelligence, structural pattern recognition, compiler construction and even text editing. Obviously, the performance of an attribute evaluation system resides in the efficiency of the syntactic and semantic subsystems. In this paper, a hardware architecture for an attribute evaluation system is presented, which is based on an efficient combinatorial implementation of Earley's parallel parsing algorithm for the syntax part of the attribute grammar. The semantic part is managed by a special purpose module that traverses the parse tree and evaluates the attributes based on a proposed stack-based approach. The entire system is described in Verilog HDL (hardware design language), in a template form that given the specification of an arbitrary attribute grammar, the HDL synthesizable source code of the system is produced on the fly by a proposed automated tool. The generated code has been simulated for validation, synthesized and tested on an Xilinx FPGA (field programmable gate arrays) board for various AGs. Our method increases the performance up to three orders of magnitude compared to previous approaches, depending on the implementation, the size of the grammar and the input string length. This makes it particularly appealing for applications where attribute evaluation is a crucial aspect, like in real-time and embedded systems. Specifically, a natural language interface is presented, based on a question-answering application from the area of airline flights.
机译:属性语法(AG)允许将上下文相关的属性添加到上下文无关的语法中,通过使用语法和语义符号来增强其表达能力,从而使它们成为大量应用程序的真正有用的工具。 AG已广泛应用于诸如人工智能,结构模式识别,编译器构建甚至文本编辑等应用程序中。显然,属性评估系统的性能取决于句法和语义子系统的效率。本文提出了一种属性评估系统的硬件体系结构,该体系结构基于Earley并行解析算法对属性语法的语法部分的有效组合实现。语义部分由一个专用模块管理,该模块遍历解析树并基于提议的基于堆栈的方法评估属性。整个系统以Verilog HDL(硬件设计语言)描述,采用模板形式(给定任意属性语法的规范),该系统的HDL可综合源代码通过提出的自动化工具即时生成。生成的代码已经过仿真,可以在各种AG的Xilinx FPGA(现场可编程门阵列)板上进行验证,合成和测试。与以前的方法相比,我们的方法将性能提高了三个数量级,这取决于实现方式,语法的大小和输入字符串的长度。这对于属性评估至关重要的应用程序特别有吸引力,例如在实时和嵌入式系统中。具体而言,基于来自航空公司领域的问答应用程序,提供了自然语言界面。

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