Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations

Shuai Shao; Peter Hailes; Tsang-Yi Wang; Jwo-Yuh Wu; Robert G. Maunder; Bashir M. Al-Hashimi; Lajos Hanzo

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Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations

机译：Turbo，LDPC和极性解码器ASIC实现的概述

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Channel coding may be viewed as the best-informed and most potent component of cellular communication systems, which is used for correcting the transmission errors inflicted by noise, interference, and fading. The powerful turbo code was selected to provi

机译：信道编码可以被视为蜂窝通信系统中信息最灵通，功能最强大的组件，可用于纠正由噪声，干扰和衰落造成的传输错误。选择强大的Turbo代码来提供

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来源
《Communications surveys & tutorials》 |2019年第3期|2309-2333|共25页
作者
Shuai Shao; Peter Hailes; Tsang-Yi Wang; Jwo-Yuh Wu; Robert G. Maunder; Bashir M. Al-Hashimi; Lajos Hanzo;
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作者单位

School of Electronics and Computer Science University of Southampton Southampton U.K.;

Department of Electrical and Computer Engineering Institute of Communication;

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原文格式 PDF
正文语种 eng
中图分类
关键词
Decoding; Parity check codes; Throughput; 5G mobile communication; 3G mobile communication; Long Term Evolution; Turbo codes;

机译：解码;奇偶校验码;吞吐量;5G移动通信;3G移动通讯;长期进化;Turbo码;

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专利

1. Design and ASIC Implementation of a 3GPP LTE- Advance Turbo Encoder and Turbo Decoder [J] . Manjunatha K N, Kiran B, Prasanna Kumar.C International Journal of Engineering Research and Applications . 2012,第4期

机译：3GPP LTE-高级Turbo编码器和Turbo解码器的设计和ASIC实现
2. Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE [J] . Studer C., Benkeser C., Belfanti S., Solid-State Circuits, IEEE Journal of . 2011,第1期

机译：用于3GPP-LTE的并行Turbo解码器ASIC的设计和实现
3. VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture [J] . Condo C., Martina M., Masera G. IEEE transactions on circuits and systems . I , Regular papers . 2013,第6期

机译：多模式Turbo / LDPC解码器架构的VLSI实现
4. A multi-standard flexible turbo/LDPC decoder via ASIC design [C] . Gentile Giuseppe, Rovini Massimo, Fanucci Luca 2010 6th International Symposium on Turbo Codes and Iterative Information Processing . 2010

机译：通过ASIC设计的多标准灵活Turbo / LDPC解码器
5. VLSI architectures for turbo code decoders, LDPC code decoders and list sphere decoders [D] . Zhang, Yuping 2007

机译：用于Turbo代码解码器，LDPC代码解码器和列表球形解码器的VLSI架构
6. An area efficient and high throughput implementation of layered min-sum iterative construction a posteriori probability LDPC decoder [O] . Hasnain Raza, Syed Azhar Ali Zaidi, Aamir Rashid, 2021

机译：分层最小和迭代构建的一个区域高效和高吞吐量的后验概率LDPC解码器
7. Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations [O] . Shuai Shao, Peter Hailes, Tsang-Yi Wang, 2019

机译：涡轮增压器，LDPC和极地解码器ASIC实现调查

Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations

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