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Using Bifurcations In The Determination Of Lock-in Ranges For Third-order Phase-locked Loops

机译:在确定三阶锁相环的锁定范围时使用分叉

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Transmission and switching in digital telecommunication networks require distribution of precise time signals among the nodes. Commercial systems usually adopt a master-slave (MS) clock distribution strategy building slave nodes with phase-locked loop (PLL) circuits. PLLs are responsible for synchronizing their local oscillations with signals from master nodes, providing reliable clocks in all nodes. The dynamics of a PLL is described by an ordinary nonlineardifferential equation, with order one plus the order of its internal linear low-pass filter. Second-order loops are commonly used because their synchronous state is asymptotically stable and the lock-in range and design parameters are expressed by a linear equivalent system [Gardner FM. Phaselock techniques. New York: John Wiley & Sons; 1979]. In spite of being simple and robust, second-order PLLs frequently present double-frequency terms in PD output and it is very difficult to adapt a first-order filter in order to cut off these components [Piqueira JRC, Monteiro LHA. Considering second-harmonic terms in the operation of the phase detector for second order phase-locked loop. IEEE Trans Circuits Syst I 2003;50(6):805-9; Piqueira JRC, Monteiro LHA. All-pole phase-locked loops: calculating lock-in range by using Evan's root-locus. Int J Control 2006;79(7):822-9]. Consequently, higher-order filters are used, resulting in nonlinear loops with order greater than 2. Such systems, due to high order and nonlinear terms, depending on parameters combinations, can present some undesirable behaviors, resulting from bifurcations, as error oscillation and chaos, decreasing synchronization ranges. In this work, we consider a second-order Sallen-Key loop filter [van Valkenburg ME. Analog filter design. New York: Holt, Rinehart & Winston; 1982] implying a third order PLL. The resulting lock-in range of the third-order PLL is determined by two bifurcation conditions: a saddle-node and a Hopf.
机译:数字电信网络中的传输和交换需要在节点之间分配精确的时间信号。商业系统通常采用主-从(MS)时钟分配策略来构建具有锁相环(PLL)电路的从节点。 PLL负责将其本地振荡与来自主节点的信号进行同步,从而在所有节点中提供可靠的时钟。 PLL的动力学由一个普通的非线性微分方程描述,阶数加其内部线性低通滤波器的阶数。通常使用二阶环路,因为它们的同步状态是渐近稳定的,并且锁定范围和设计参数由线性等效系统表示[Gardner FM。锁相技术。纽约:John Wiley&Sons; 1979]。尽管简单而稳健,但是二阶PLL在PD输出中经常出现双频项,并且很难采用一阶滤波器来切断这些分量[Piqueira JRC,Monteiro LHA​​。在二阶锁相环的鉴相器操作中考虑二次谐波项。 IEEE Trans Circuits Syst I 2003; 50(6):805-9; Piqueira JRC,蒙泰罗LHA。全极锁相环:通过使用Evan的根轨迹来计算锁定范围。 Int J Control 2006; 79(7):822-9]。因此,使用了高阶滤波器,从而导致阶数大于2的非线性环路。由于高阶和非线性项(取决于参数组合),此类系统可能会由于分叉而表现出一些不良行为,例如误差振荡和混沌。 ,减小同步范围。在这项工作中,我们考虑了二阶Sallen-Key环路滤波器[van Valkenburg ME。模拟滤波器设计。纽约:霍尔特,雷内哈特和温斯顿; [1982年]暗示三阶PLL。三阶PLL的最终锁定范围由两个分叉条件决定:鞍形节点和Hopf。

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