Novel Analog Calibration Technique for Current-Steering DACs' Dynamic Performance

摘要

This paper reports the post-layout dynamic performance of a novel calibration technique for current-steering digital-to-analog converter that was proposed previously. This technique not only improves the linearity, but it does so with low power as well as a very low area. It uses an analog feedback loop consisting of four transistors to calibrate each bit of the DAC, and the same feedback circuit is used for all the bits, thus significantly saving the chip area. Layout of the 10-bit calibrated CS DAC circuit was done in a 180-nm technology; the total area of the DAC and the calibration circuit together was 0.16 . Simulation results show that the spurious free dynamic range is 62 dB for signals of 1 MHz at a sampling frequency of 100 MS/s.