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Theory of Expansion Boolean Algebra and Its Applications in CMOS VLSI Digital Systems

机译:布尔布尔代数理论及其在CMOS VLSI数字系统中的应用

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Based on the relationship between circuits (systems) and the signals in the circuits (systems), the theory of expansion Boolean algebra is presented in this paper. Static complementary logic circuits and static pass transistors logic circuits have been used to implement the high-speed and low-power-consumption cells circuits in CMOS VLSI systems. It is important to study the extraction method of logic expressions for these types of circuits. By analyzing the operations principles of MOS transistors in CMOS circuits, the theory of expansion Boolean algebra of CMOS logical circuits is presented. Based on the algebraic theory, a method of extracting the logic expressions from the two types of CMOS logical circuits is derived. On the basis of the method, a switch-level design method of CMOS logic circuits based on the algebra theory is presented, and the design method is used to design the high-speed and low-power full adder cells in CMOS VLSI systems. By the results of the simulation experiments, it is shown that the pass transistors and transmission gates hybrid CMOS full adder circuits proposed in this paper have a lower power-delay product by comparison with the full adder circuits designed by using other methods.
机译:基于电路(系统)与电路(系统)中信号之间的关系,提出了扩展布尔代数的理论。静态互补逻辑电路和静态传输晶体管逻辑电路已被用于实现CMOS VLSI系统中的高速和低功耗单元电路。研究这些类型的电路的逻辑表达式的提取方法很重要。通过分析CMOS电路中MOS晶体管的工作原理,提出了CMOS逻辑电路的布尔布尔代数理论。基于代数理论,推导了从两种类型的CMOS逻辑电路中提取逻辑表达式的方法。在此方法的基础上,提出了一种基于代数理论的CMOS逻辑电路的开关级设计方法,并利用该设计方法设计了CMOS VLSI系统中的高速,低功耗全加法器单元。仿真实验结果表明,与采用其他方法设计的全加法器电路相比,本文提出的传输晶体管和传输门混合CMOS全加法器电路具有较低的功率延迟乘积。

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