Reduced-Complexity Polynomials with Memory Applied to the Linearization of Power Amplifiers with Real-Time Discrete Gain Control

摘要

In reconfigurable power amplifiers (PAs), the efficiency can be improved by dynamically switching the discrete gain mode according to the input envelope amplitude. Nevertheless, discontinuities that occur between gain mode changes critically compromise the linearization capability of traditional digital baseband predistorters (DPDs) based on continuous polynomials with memory. To circumvent such drawback, this work introduces a model based on polynomials bounded at both sides and able to take into account commutation delays. Besides, two novel approaches are presented to the model order reduction without basis change. The effectiveness of the proposed approaches to linearize a 130nm CMOS class AB PA commutating in real time among three gain modes is certified based on Cadence Virtuoso and Matlab simulations. The proposed memory polynomial-based model was able to accurately model both direct and inverse transfer characteristics of a three gain mode PA, showing normalized mean square error results of about -41dB. Besides, a 25.5dB reduction in adjacent channel power ratio is provided by the inclusion of a 10 parameters DPD that adopts the proposed approaches, in comparison with unlinearized PA of same output mean power.