Concurrent Tri-band CMOS Power Amplifier Linearized by 3D Improved Memory Polynomial Digital Predistorter

摘要

This paper presents the design and post-layout results of a 5G power amplifier (PA) in 130 nm CMOS technology. The circuit incorporates a pre-amplification stage that uses a current reuse technique followed by a power stage. The PA operates in the 2-5 GHz range, with a power gain of 16-20.9 dB, output saturation power of 19.1-21.7 dBm, an output compression point of 15.8-20.4 dBm and maximum power-added efficiency of 9.28-22.4%. A three-dimensional improved memory polynomial (3DIMP) and a three-dimensional harmonic improved memory polynomial (3DHIMP) are introduced to the behavioral modeling and digital baseband predistortion of the designed PA for the cases without and with multiplicity among carriers, respectively. Moreover, an ascendant factor algorithm is presented for selecting the truncation factors. Simulation results adopting IEEE 802.11n at channel 1, LTE at channel 2 and IEEE 802.11ac at channel 3 show that the proposed 3DIMP and 3DHIMP, in comparison with previous three-dimensional multi-band (3DMB) and three-dimensional harmonic memory polynomial (3DHMP) having the same amount of parameters, can improve the normalized mean square error by up to 8.3 dB and 16.6 dB, respectively, when applied to the PA inverse behavioral modeling. Additional reductions in error vector magnitude up to 0.39 p.p. and 1.23 p.p. are also achieved when the 3DIMP and 3DHIMP are responsible for the PA linearization instead of previous 3DMB and 3DHMP, respectively.