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Area-Efficient Dual-Mode Fused Floating-Point Three-Term Adder

机译:面积高效的双模融合浮点三项加法器

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Floating-point addition is the most frequently used arithmetic operation in almost all general-purpose processors. This paper presents a dual-mode architecture for fused floating-point three-term adder. The traditional architecture for fused floating-point three-term adder is single-mode design where the addition of three operands takes place in a single unit. The existing improved architecture is also a single-mode design that incorporates few optimizations compared to the traditional fused floating-point three-term adder that would reduce area as well as delay. The proposed dual-mode architecture performs either a double-precision addition or two parallel single-precision additions in a single architecture based on the mode selection. The proposed architecture supports both normal and subnormal operations and also exceptional case handling like infinity, NaN and zero cases. The proposed architecture is implemented using both FPGA and ASIC, thus leading to efficient resource sharing, and the area gets reduced compared to two single-precision and a double-precision traditional and improved floating-point adder architectures.
机译:在几乎所有通用处理器中,浮点加法是最常用的算术运算。本文提出了一种用于融合浮点三项加法器的双模式架构。融合浮点三项加法器的传统体系结构是单模式设计,其中三个操作数的加法发生在单个单元中。现有的改进架构也是一种单模设计,与传统的融合浮点三项加法器相比,它几乎没有优化,可以减少面积和延迟。所提出的双模式体系结构基于模式选择在单个体系结构中执行双精度加法或两个并行的单精度加法。所提出的体系结构支持正常和次正常操作以及异常情况处理,例如无穷大,NaN和零大小写。所提出的体系结构同时使用FPGA和ASIC来实现,从而实现了有效的资源共享,并且与两个单精度和双精度的传统和改进的浮点加法器体系结构相比,面积得以减小。

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