The conventional implementation of shift registers systems such asnlinear feedback shift registers (LFSR) suffers from two major drawbacks:n1) all the elements in the structure are clocked during each clock cyclenand 2) the throughput is limited to only one bit per clock cycle.nSequence generators implemented using this architecture dissipate ansignificant amount of power when clocked at high frequency. This isndetrimental to the operation of low-power communication equipment andnbattery operated systems. This paper presents an architecture and annalgorithm for the parallel implementation of digital sequences and shiftnregister systems in general. The advantages of the parallel architecturenare: 1) reduced power dissipation, and 2) higher throughput rate.nHowever the implementation of sequence generators using thisnarchitecture requires a number of switches of the order of N (the lengthnof the shift register) times M (the number of taps) between the registernand the XOR tree making this implementation impractical. We present annalgorithm which reduces this number to the order of N+M thus making thisnapproach practical. The parallel architecture is characterized by itsnflexibility to provide more than one bit of output with the accompanyingnadvantage of operating with a higher throughput at a lower clock rate tonfurther reduce the power dissipation
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