An expression is obtained for the output floating-point roundoffnnoise variance of a general Nth-order state-space digital filter withnzero-mean white noise input signal. This expression is then simplifiednfor the case there the filter is implemented on a floating-point digitalnsignal processor. Such processors carry extended precision bits in thenaccumulation register, so that the primary source of roundoff error innthe output arises from the final quantization of the mantissa. Undernthis condition of extended precision during multiply-accumulate, it isnfound that the floating-point roundoff noise gain is identical to thenfixed-point roundoff noise gain used extensively in the past forndesigning optimal and near-optimal fixed-point digital filters.nTherefore, previous work to optimize fixed-point realizations isndirectly applicable to the floating-point realizations. This conclusionnis verified by actual roundoff noise measurements using a digital signalnprocessor simulator. Since floating-point digital filters do not requirenscaling, optimal floating-point realizations require N fewer multipliesnthan fixed-point filters. Simple design equations are presented for thenfloating-point minimum-noise second-order state-space structure with twontrivial unity multiplies
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