Analysis of ground-bounce induced substrate noise coupling in a lowresistive bulk epitaxial process: design strategies to minimize noiseeffects on a mixed-signal chip

摘要

The industry trend toward system-on-chip solutions continues tonpush the limits of mixed-signal design. Increasing the integration ofnanalog and digital circuitry causes a struggle to maintain analog signalnintegrity. Digital switching of noise coupling through the commonnsubstrate is both difficult to measure and difficult to control. Thisnpaper introduces and applies a practical first-order simulationnmethodology for performing a substrate noise analysis in a low resistivenbulk process. Although this subject has been analyzed in numerousnjournal articles, few have applied their analysis method to a whole-chipndesign. This SPICE model will allow mixed-signal designers to determinendesign variables that will minimize substrate noise. This worknelaborates on key aspects of substrate noise that available referencesndo not handle adequately, including: sources of substrate noise,ndetermination of power-rail and bulk-resonance frequencies, andnalternatives for bulk biasing. The new model is used to analyzenMotorola's 56824, the latest low-cost 16-bit digital signal processorndesign. The analysis includes the determination of: (1) the on-chip busnand I/O bus noise coupled to the substrate; (2) the dominant resonantnfrequencies in the chip; and (3) the best bulk-biasing alternative