Point-to-point connectivity between neuromorphic chips usingaddress events

摘要

This paper discusses connectivity between neuromorphic chips,nwhich use the timing of fixed-height fixed-width pulses to encodeninformation. Address-events (log2(N)-bit packets thatnuniquely identify one of N neurons) are used to transmit these pulses innreal time on a random-access time-multiplexed communication channel.nActivity is assumed to consist of neuronal ensembles-spikes clustered innspace and in time. This paper quantifies tradeoffs faced in allocatingnbandwidth, granting access, and queuing, as well as throughputnrequirements, and concludes that an arbitered channel design is the bestnchoice. The arbitered channel is implemented with a formal designnmethodology for asynchronous digital VLSI CMOS systems, afternintroducing the reader to this top-down synthesis technique. Followingnthe evolution of three generations of designs, it is shown how thenoverhead of arbitrating, and encoding and decoding, can be reduced innarea (from N to √N) by organizing neurons into rows and columns,nand reduced in time (from log2(N) to 2) by exploitingnlocality in the arbiter tree and in the row-column architecture, andnclustered activity. Throughput is boosted by pipelining and by readingnspikes in parallel. Simple techniques that reduce crosstalk in thesenmixed analog-digital systems are described