首页> 外文期刊>IEEE transactions on circuits and systems. II, Express briefs >A gigabit multidrop serial backplane for high-speed digital systems based on asymmetrical power splitter
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A gigabit multidrop serial backplane for high-speed digital systems based on asymmetrical power splitter

机译:基于非对称功率分配器的千兆位多点串行背板,用于高速数字系统

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The maximum data rate in today's available multidrop backplanes is significantly limited due to signal integrity concerns. In this brief, a novel gigabit multidrop serial link configuration for high-speed digital systems based on newly developed asymmetrical broadband power splitters with matching trace impedance, is presented. The proposed power splitter features good impedance match at all ports without the insertion losses being inherent to common resistive power splitters. Experimental results obtained from implemented prototypes demonstrate a satisfactory operation of the proposed multidrop serial backplane for a data rate above 3.5 Gbps.
机译:由于信号完整性问题,当今可用的多点背板中的最大数据速率受到很大限制。在本简介中,提出了一种新的用于高速数字系统的千兆位多点串行链路配置,该配置基于新开发的具有匹配走线阻抗的非对称宽带功率分配器。所提出的功率分配器在所有端口均具有良好的阻抗匹配,而普通电阻式功率分配器固有的插入损耗却没有。从已实现的原型获得的实验结果证明了所提出的多点串行背板对于3.5 Gbps以上的数据速率具有令人满意的操作。

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