A 1–16-Gb/s Wide-Range Clock/Data Recovery Circuit With a Bidirectional Frequency Detector

摘要

A 1–16-Gb/s wide-range clock and data recovery (CDR) circuit is presented by using the proposed bidirectional frequency detector. This CDR circuit is fabricated in 0.13-$mu hbox{m}$ CMOS technology, and its active area is 0.134 $ hbox{mm}^{2}$ without a loop filter. The power consumption of this CDR circuit is 160 mW for a supply of 1.5 V. A modified interpolation voltage-controlled oscillator is presented, which covers from 4.9 to 10.2 GHz. A quadrature divider is used to generate accurate quadrature clocks.