Clock- and Data-Recovery Circuit With Independently Controlled Eye-Tracking Loop for High-Speed Graphic DRAMs

摘要

An independently controlled eye-tracking clock- and data-recovery (CDR) circuit that achieves enhanced high-frequency jitter tolerance is presented in this brief. In the proposed CDR, a data-tracking loop compensates interchannel timing skews and rejects low-frequency jitter of the data, and an eye-tracking loop tracks asymmetric jitter distribution and high-frequency jitter of the data to enhance high-frequency jitter tolerance. This can be achieved by independently controlling two loops in the digital domain. The CDR is implemented using an 0.18- $muhbox{m}$ CMOS process, and a bit error rate of less than $10^{-12}$ was achieved for a data rate up to 5.8 Gb/s using a $2^{31} - 1$ pseudorandom binary-sequence input.