A low-jitter wide-range skew-calibrated dual-loop DLL usingantifuse circuitry for high-speed DRAM

摘要

This paper describes a delay-locked loop (DLL) circuit having twonadvancements, a dual-loop operation for a wide lock range andnprogrammable replica delays using antifuse circuitry and internalnvoltage generator for a post-package skew calibration. The dual-loopnoperation uses information from the initial time difference betweennreference clock and internal clock to select one of the differentialninternal loops. This increases the lock range of the DLL to the lowernfrequency. In addition, incorporation of the programmable replica delaynusing antifuse circuitry and the internal voltage generator allows fornthe elimination of skews between external clock and internal clock thatnoccur from on-chip and off-chip variations after the package process.nThe proposed DLL, fabricated on 0.16-Μm DRAM process, operates overnthe wide range of 42-400 MHz with 2.3-V power supply. The measurednresults show 43-ps peak-to-peak jitter and 4.71-ps rms jitter consumingn52 mW at 400 MHz