A low-jitter mixed-mode DLL for high-speed DRAM applications

摘要

This paper presents a salient clock deskewing method with anmixed-mode delay-locked loop (MDLL) for high-speed synchronous DRAMnapplications. The presented method not only solves the resolutionnproblem of conventional digital deskewing circuits, but also improvesnthe jitter performance to the level of well-designed analog deskewingncircuits, while keeping the power consumption and locking speed ofndigital deskewing circuits. The whole deskewing circuit is fabricated inna 3.3-V 0.6-Μm triple-metal CMOS process and occupies a die area ofn0.45 mm2. Measured rms jitter is 6.38 ps. The powernconsumption of the entire chip, including I/O peripherals, is 33 mW atn200 MHz with a 3.3-V supply