Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits

摘要

Clock skew is a major cause of severe timing yield degradation for sub-ear-threshold digital circuits. We report for the first time on employing hot-carrier injection (HCI) for post-silicon clock-deskew trimming. An HCI trimmed clock buffer, which can be individually selected and stressed to adjust the clock edge, is proposed. In addition, it can be used in conjunction with on-chip skew monitoring circuits to achieve auto-stressing. Our approach is proven to be effective through a representative 1.1-mm $times$ 0.8-mm clock tree in a 40-nm high-$k$ complimentary metal–oxide–semiconductor process. On average, it reduces the clock skew by eight times at 0.4 V $V_{rm dd}$. No significant recovery is noticed two weeks after trimming.