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A Low-Cost MMSE-SIC Detector for the MIMO System: Algorithm and Hardware Implementation

机译:MIMO系统的低成本MMSE-SIC检测器:算法和硬件实现

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We consider the minimum mean-squared error with successive interference cancellation (MMSE-SIC) detection of a frame of data in the spatially multiplexed multiple-input–multiple-output (MIMO) system. A complete MMSE-SIC detector needs to compute at both the preprocessing and SIC-detection stages. Since the SIC detection, which can be regarded as a backward substitution, is inevitable, we develop a computationally efficient preprocessing algorithm that relies on the backward substitution. We then propose a low-cost hardware architecture with a commonly shared backward-substitution module to work at both the preprocessing and detection stages. The very-large-scale-integration implementation results of our architecture for the four-by-four MIMO system using the 0.18-$muhbox{m}$ complementary metal–oxide–semiconductor technology reveal that our architecture requires the fewest 79-K gates, provides the high throughput rate of 416 Mb/s, and works with the smallest preprocessing latency of 64 clock cycles. Our MMSE-SIC detector is a cheap solution for MIMO detection.
机译:我们考虑了在空间多路复用多输入多输出(MIMO)系统中对数据帧进行连续干扰消除(MMSE-SIC)检测的最小均方误差。完整的MMSE-SIC检测器需要在预处理和SIC检测阶段进行计算。由于SIC检测(可以视为反向替换)是不可避免的,因此我们开发了一种依赖于反向替换的高效计算预处理算法。然后,我们提出了一种低成本的硬件体系结构,该体系结构具有一个共同共享的后向替换模块,可以同时在预处理和检测阶段使用。我们使用0.18- $ muhbox {m} $互补金属-氧化物-半导体技术的四乘四MIMO系统的架构的大规模集成实现结果表明,我们的架构需要最少的79-K门,提供416 Mb / s的高吞吐率,并以64个时钟周期的最小预处理延迟工作。我们的MMSE-SIC检测器是MIMO检测的廉价解决方案。

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