System and method of efficiently implementing secure hash algorithm (SHA-1) in digital hardware that accomplishes optimal computation speed using minimal hardware resources

摘要

A method of completing the Secure Hash Algorithm (SHA-1) computation in exactly 81 clock cycles with digital hardware. The general implementation techniques include: using a combination of synchronous storage elements to store the required computation values and asynchronous circuits to perform all the logic and mathematic operations of each step of the 81-step SHA-1 computation within a single clock cycle; using a quad-output-channel 16×32-bit circular queue memory to store the 512-bit message segment (block), as a computation buffer of the Wt parameter, and to supply the Wt-3, Wt-8, Wt-14, and Wt-16 data parameters simultaneously; using a combination of a counter circuit and a decoder/encoder circuit to control selecting data parameters and sequencing the 81-step SHA-1 computation; and using an automated controller to control internal units that perform SHA-1 and allowing external systems to access the SHA-1 computation service. The robust architecture allows for a highly efficient digital hardware implementation.