A 10-Mbps 0.8-pJ/bit Referenceless Clock and Data Recovery Circuit for Optically Controlled Neural Interface System

摘要

We propose a low-voltage low-power clock and data recovery (CDR) circuit which incorporates a relaxation-based voltage-controlled oscillator and clock-edge modulation, which eliminates the need for an external reference clock without allowing harmonic locking. This CDR supports input data rates between 200 kbps and 10 Mbps at 0.7 V and operates up to 24 MHz at 1.0 V. The proposed design consumes 8 $muhbox{W}$ at an input data rate of 10 Mbps and achieves 0.8 pJ/bit of energy per bit even though the circuit is implemented in a 0.18-$muhbox{m}$ CMOS technology.