A Calibration Technique for Pipelined ADCs Using Self-Measurement and Histogram-Based Test Methods

摘要

This brief presents a digital background calibration technique for pipelined analog-to-digital converters (ADCs) to correct the capacitor mismatch, finite dc gain, and nonlinearity of residue amplifiers. It estimates the calibration coefficients at start-up by a modified self-measurement method with low-precision stimulation signals in the multistage calibration. Then, during the ADC normal operation, a sliding histogram in the vicinity of the decision boundaries of stage comparators is utilized to adjust the calibration coefficients in order to follow the variation of errors. To do so, the ratio of information achieved from the initial and new histograms is used to update the calibration coefficients. Behavioral simulation results of a 12-bit pipelined ADC show that the proposed calibration technique improves the ADC linearity by more than 4 bits and it is robust against the variation of errors.