A Novel Digital Duty-Cycle Modulation Scheme for FPGA-Based Digital-to-Analog Conversion

摘要

In this brief, a novel (DDCM) scheme is outlined. The digital part, embedded in a field-programmable gate array (FPGA) chip, consists of a lookup DDCM map, a dual DDCM counting logic with interrupt service routines, and a holder. It is used as a building core of a well-tested 10–12 bits FPGA-based digital-to-analog converter (DAC). Experimental tests show that for a digital input bandwidth of 3 kHZ, the new DDDM technique for DAC achieves 40 dBc of surpious free dynamic range and 60 dB of NOISE FLOOR range. This performance is a challenge compared with most low cost oversampling DACs schemes with single decimation stage.