Digital Background Calibration for Pipelined ADCs Based on Comparator Decision Time Quantization

摘要

This brief presents a digital background calibration technique that embraces comparator decision time to calibrate interstage gain errors and capacitor mismatches in pipelined analog-to-digital converters (ADCs). It does not modify the original analog signal path except for the addition of a comparator decision time binary quantizer built by simple digital gates. The technique does not limit either the ADC input signal swing or bandwidth. Simulation results for a 12-bit pipelined ADC show that the proposed technique can improve the signal- to-noise-and-distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) from 44 and 48 dB to 72 and 86 dB, respectively. The SNDR convergence time is less than cycles.