A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI

摘要

Resilient design is a promising approach to mitigate the performance losses resulting from process, voltage, and temperature variations and benefits from average-case path activity. Many such design techniques rely on error-detecting latches (EDLs) to identify timing errors. This brief presents a novel low-power low-area EDL that achieves 31.8% less energy consumption, 15.8% less leakage, and 35.4% less area compared with the most efficient previous designs, reducing the overhead and thereby increasing the potential benefits of resilient designs.