Low-Power, Low-Area Multi-level 2-D Discrete Wavelet Transform Architecture

摘要

This paper introduces an efficient, low-power, low-area multi-level 2-D discrete Haar wavelet transform (2-D DHWT) architecture. The proposed architecture consists of four add/subtract elements, register bank, three multiplexers and a buffer memory. All or fractions of theN-stage register are used to perform row-column image transposition for every 2-D DHWT decomposition level. A fixed size block memory of N/2 x N/2-sample is used to store low-low frequency band to perform multi-level 2-D DHWT decomposition, except for the first level where no block memory is used. For synthesis results, the proposed architecture outperforms similar architectures in hardware usage, power consumption and speed. Also, it is found that the power delay product of the proposed architecture is less than 1 (mW x mu s) compared with up to 1.9 (mW x mu s) for cascaded architecture. Furthermore, an up to 209MHzprocessing speed is achieved which enables a three-level 2-DDHWTdecomposition of a 256x256-pixel image to be performed within 0.4ms.