Macromodels for Static Virtual Ground Voltage Estimation in Power-Gated Circuits

摘要

Static virtual ground voltage is an important parameter to be accurately and efficiently estimated for fine-grained power gating in logic circuits. Previous work results in a large error in estimation due to conservative leakage models and inaccurate assumption of voltage conditions at the input of CMOS gates in power-gated circuits. To overcome these problems, we propose support vector machine (SVM)-based macromodels to estimate the leakage current of CMOS gates and thus achieve effective reduction in error in leakage model characterization. These models are then used in SVM classifier (SVC) and regressor to formulate an SVM regression-based model. The SVC results in 3 savings in data generation time compared with HSPICE simulation to develop the final model. The proposed model results in < 1% error and 23 000 times the speedup than HSPICE for the largest benchmark circuit.