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首页> 外文期刊>Circuits and Systems II: Express Briefs, IEEE Transactions on >A 1.5-to-3.0GHz Tunable RF Sigma-Delta ADC With a Fixed Set of Coefficients and a Programmable Loop Delay
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A 1.5-to-3.0GHz Tunable RF Sigma-Delta ADC With a Fixed Set of Coefficients and a Programmable Loop Delay

机译:1.5至3.0GHz可调调谐RF Sigma-Delta ADC,具有固定系数和可编程环延迟

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摘要

In this brief, we present a tunable bandpass RF Sigma-Delta modulator with a fixed set of feedback DAC coefficients. The sampling frequency, f(s), is tuned with the center frequency, f(0), in order to maintain a fixed normalized center frequency, f(0)/fs. Any variation in the loop delay is compensated to maintain a fixed normalized loop-delay t(d)/T-s. The bandpass Sigma-Delta, reported in this brief, is based on an LC resonator with tunable center frequency from 1.5 to 3.0 GHz and a corresponding sampling frequency from 6.0 to 12.0 GHz. For an oversampling ratio of 64, the ADC achieves the same SNDR of 37 dB and the same Dynamic Range of 45 dB over the complete tuning range. This performance is achieved for a bandwith of 47 MHz at 1.5GHz and a Bandwidth of 93 MHz at 3 GHz. The ADC, fabricated in a 65 nm CMOS process, consumes only 13 mW from a 1.2 V supply. In order to compare this circuit with the state of the art, we use not only the conventional ADC Figure of Merit but we also use a Figure of Merit dedicated to RF circuits. In this case, the measured chip center frequency, noise figure and non-linearity are also taken into account in the comparison.
机译:在此简介中,我们介绍了一种可调谐带通RF Sigma-Delta调制器,其具有固定的反馈DAC系数。采样频率f(s),用中心频率,f(0)调谐,以便维持固定的归一化中心频率f(0)/ fs。回路延迟中的任何变化都被补偿以维持固定的归一化环延迟T(d)/ t-s。在此简介中报告的带通Sigma-Delta基于LC谐振器,可调谐中心频率为1.5到3.0 GHz,相应的采样频率为6.0至12.0 GHz。对于64的过采样比例,ADC在完全调谐范围内实现了37 dB的相同SND,相同的动态范围为45 dB。对于47 MHz的带,在1.5GHz处实现这种性能,并且在3 GHz的带宽为93 MHz。在65nm CMOS工艺中制造的ADC,从1.2 V电源消耗13兆瓦。为了将该电路与现有技术进行比较,我们不仅使用传统的ADC的优点形式,但我们也使用专用于RF电路的优点。在这种情况下,在比较中也考虑了测量的芯片中心频率,噪声系数和非线性。

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