Nano- and micro-filled conducting adhesives for z-axis interconnections: new direction for high-speed, high-density, organic microelectronics packaging

摘要

Purpose - The purpose of this paper is to discuss the use of epoxy-based conducting adhesives in z-axis interconnections. Design/methodology/approach - A variety of conductive adhesives with particle sizes ranging from 80 nm to 15 μm were laminated into printed wiring board substrates. SEM and optical microscopy were used to investigate the micro-structures, conducting mechanism and path. The mechanical strength of the various adhesives was characterized by 90° peel test and measurement of tensile strength. Reliability of the adhesives was ascertained by IR-reflow, thermal cycling, pressure cooker test (PCT), and solder shock. Change in tensile strength of adhesives was within 10 percent after 1,000 cycles of deep thermal cycling (DTC) between -55 and 125°C. Findings - The volume resistivity of copper, silver and low-melting point (LMP) alloy based paste were 5 x 10~-4,5 x 10~-5and 2 x 10~-5 Ωcm, respectively. Volume resistivity decreased with increasing curing temperature. Adhesives exhibited peel strength with Gould's JTC-treated Cu as high as 2.75 lbs/in, for silver, and as low as 1.00 Ib/in. for LMP alloy. Similarly, tensile strength for silver, copper and LMP alloy were 3,370, 2,056 and 600 ψ, respectively. There was no delamination for silver, copper and LMP alloy samples after 3X IR-reflow, PCT, and solder shock. Among all, silver-based adhesives showed the lowest volume resistivity and highest mechanical strength. It was found that with increasing curing temperature, the volume resistivity of the silver-filled paste decreased due to sintering of metal particles. Research limitations/applications - As a case study, an example of silver-filled conductive adhesives as a z-axis interconnect construction for a flip-chip plastic ball grid array package with a 150μm die pad pitch is given. Originality/value - A high-performance Z-interconnect package can be provided which meets or exceeds JEDEC level requirements if specific materials, design, and manufacturing process requirements are met, resulting in an excellent package that can be used in single and multi-chip applications. The processes and materials used to achieve smaller feature dimensions, satisfy stringent registration requirements, and achieve robust electrical interconnections are discussed.