Structural Optimization Of Hftisio High-k Gate Dielectrics By Utilizing In-situ Pvd-based Fabrication Method

摘要

We investigated the optimum structure for Ti-containing Hf-based high-k gate dielectrics to achieve EOT scaling below 1 nm. TiO_2/HfSiO/SiO_2 trilayer and HfTiSiO/SiO_2 bilayer structures were fabricated by a newly developed in-situ PVD-based method. We found that thermal diffusion of Ti atoms to SiO_2 underlayers degrades the EOT-J_g characteristics. Our results clearly demonstrated the impact of the trilayered structure with TiO_2 capping for improving EOT-J_g characteristics of the gate stack. We achieved an EOT scaling of 0.78 nm as well as reduced gate leakage of 7.2 × 10~(-2) A/cm~2 fair a TiO_2/HfSiO/SiO_2 trilayered high-k dielectric while maintaining the electrical properties at the bottom interface.