Performance of Josephson array systems related to fabrication techniques and design

摘要

Arrays of Nb/Al/sub 2/O/sub 3//Nb Josephson tunnel junctions show dc characteristics of high quality when the trilayer is deposited direct on polished Si wafers. Underlayers such as rf-sputtered SiO/sub 2/, can considerably degrade the junction parameters. These results suggest that voltage standard chips should be produced with a cover instead of a groundplane. First results of attenuation measurements on such circuits are presented and discussed. Furthermore, a new and more simple fabrication process without a window-insulating layer and only two photolithographic steps is presented. Arrays of several thousands of junctions showed no problems of any kind with trapped flux.