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Improved Fabrication Yield for 10-V Programmable Josephson Voltage Standard Circuit Including 524288 NbN/TiN/NbN Josephson Junctions

机译:包括524288 NbN / TiN / NbN Josephson结的10V可编程Josephson电压标准电路的改进制造良率

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A 10-V programmable Josephson voltage standard (PJVS) circuit including 524 288 vertically stacked NbN/TiN/NbN Josephson junctions was successfully fabricated without any defects. The chip was cooled with a compact cryocooler at a temperature of 9.8 K and generated an output voltage of 17.3 V with the first Shapiro step height of 1.0 mA under microwave irradiation at 16 GHz. Furthermore, the circuit design having the high output voltage increased the number of available chips for the 10-V PJVS. The fabrication yield for the chip, which generates greater than 10 V, was 36%, which is ten times greater than that for a perfect chip without any defects. This method was not effective for the chip that had serious defects, such as a disconnection across the array or short between the array and ground; thus, efforts to reduce such defects, e.g., frequent maintenance inside vacuum chambers for film preparation and etching, were found to be essential.
机译:包括524 288个垂直堆叠的NbN / TiN / NbN Josephson结的10V可编程约瑟夫森电压标准(PJVS)电路已成功制造,没有任何缺陷。在紧凑的低温冷却器中,将芯片在9.8 K的温度下冷却,并在16 GHz的微波辐射下,产生的输出电压为17.3 V,第一Shapiro台阶高度为1.0 mA。此外,具有高输出电压的电路设计增加了10V PJVS可用芯片的数量。产生大于10 V的芯片的制造良率为36%,比没有缺陷的完美芯片的制造良率高十倍。这种方法对存在严重缺陷的芯片(例如,阵列之间的断开连接或阵列与地面之间的短路)无效。因此,发现减少这种缺陷的努力是必需的,例如,经常在真空室内进行维护以进行膜制备和蚀刻。

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