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A novel approach for the improvement of electrostatic behaviour of physically doped TFET using plasma formation and shortening of gate electrode with hetero-gate dielectric

机译:利用等离子体形成和利用异质栅介质缩短栅电极来改善物理掺杂TFET静电行为的新方法

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摘要

This article presents a new device configuration to enhance current drivability and suppress negative conduction (ambipolar conduction) with improved RF characteristics of physically doped TFET. Here, we used a new approach to get excellent electrical characteristics of hetero-dielectric short gate source electrode TFET (HD-SG SE-TFET) by depositing a metal electrode of 5.93 eV work function over the heavily doped source (P+) region. Deposition of metal electrode induces the plasma (thin layer) of holes under the Si/HfO2 interface due to work function difference of metal and semiconductor. Plasma layer of holes is advantageous to increase abruptness as well as decrease the tunneling barrier at source/channel junction for attaining higher tunneling rate of charge carriers (i.e., electrons), which turns into 86.66 times higher ON-state current compared with the conventional physically doped TFET (C-TFET). Along with metal electrode deposition, gate electrode is under-lapped for inducing asymmetrical concentration of charge carriers in the channel region, which is helpful for widening the tunneling barrier width at the drain/channel interface. Consequently, HD-SG SE-TFET shows suppression of ambipolar behavior with reduction in gate-to-drain capacitance which is beneficial for improvement in RF performance. Furthermore, the effectiveness of hetero-gate dielectric concept has been used for improving the RF performance. Furthermore, reliability of C-TFET and proposed structures has been confirmed in term of linearity.
机译:本文提出了一种新的器件配置,以增强电流可驱动性并通过改善物理掺杂TFET的RF特性来抑制负导通(双极导通)。在这里,我们通过在重掺杂源(P +)区域上沉积功函数为5.93 eV的金属电极,获得了异质电介质短栅源电极TFET(HD-SG SE-TFET)的出色电特性。由于金属和半导体的功函数不同,金属电极的沉积会在Si / HfO2界面下方引起空穴的等离子体(薄层)。空穴的等离子体层有利于增加突变率并减小源/沟道结处的隧穿势垒,以实现更高的电荷载流子(即电子)隧穿速率,与传统的物理方式相比,其导通态电流高出86.66倍掺杂的TFET(C-TFET)。与金属电极沉积一起,对栅极电极进行重叠研磨,以在沟道区域中引起载流子的不对称集中,这有助于加宽漏极/沟道界面处的隧穿势垒宽度。因此,HD-SG SE-TFET在抑制栅极到漏极电容的同时,抑制了双极性行为,这有利于改善RF性能。此外,异质栅电介质概念的有效性已被用于改善RF性能。此外,已经在线性方面证实了C-TFET和提出的结构的可靠性。

著录项

  • 来源
    《Applied Physics》 |2018年第4期|306.1-306.10|共10页
  • 作者单位

    Indian Inst Informat Technol Design & Mfg, PDPM, Jabalpur, India;

    Indian Inst Informat Technol Design & Mfg, PDPM, Jabalpur, India;

    Indian Inst Informat Technol Design & Mfg, PDPM, Jabalpur, India;

    Indian Inst Informat Technol Design & Mfg, PDPM, Jabalpur, India;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
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