首页> 外国专利> The phase which forms the gate dielectric film in formation manner of the polysilicon gate where the germanium of the MOS transistor dopes and the formation mannered null substrate

The phase which forms the gate dielectric film in formation manner of the polysilicon gate where the germanium of the MOS transistor dopes and the formation mannered null substrate

机译:以多晶硅栅极的形成方式形成栅极介电膜的相,其中掺杂了MOS晶体管的锗和形成的空衬底

摘要

A method of forming polycrystalline silicon germanium gate electrode is disclosed. The method include the steps of forming gate insulation layer on a substrate, forming a polycrystalline silicon layer on the gate insulation layer and making a plasma doping of germanium to the polycrystalline silicon layer. Generally, boron is doped to the polycrystalline silicon after the step of the plasma doping of germanium. The process of plasma doping of germanium comprises the step of forming germanium contained plasma and enhancing bias electric potential to substrate for the formulated germanium plasma to be accelerated and injected to the polycrystalline silicon layer revealed. If the present invention is applied to CMOS transistor device, doping mask for the germanium plasma doping can be used.
机译:公开了一种形成多晶硅锗栅电极的方法。该方法包括以下步骤:在基板上形成栅极绝缘层;在栅极绝缘层上形成多晶硅层;以及对多晶硅层进行锗的等离子体掺杂。通常,在锗的等离子体掺杂步骤之后,将硼掺杂到多晶硅中。锗的等离子体掺杂工艺包括以下步骤:形成含锗的等离子体,并增强对衬底的偏置电势,以使所配制的锗等离子体被加速并注入到露出的多晶硅层中。如果将本发明应用于CMOS晶体管器件,则可以使用用于锗等离子体掺杂的掺杂掩模。

著录项

  • 公开/公告号JP4633310B2

    专利类型

  • 公开/公告日2011-02-23

    原文格式PDF

  • 申请/专利权人

    申请/专利号JP20010363395

  • 发明设计人

    申请日2001-11-28

  • 分类号H01L21/28;H01L21/336;H01L21/265;H01L21/3215;H01L21/8238;H01L27/092;H01L29/78;

  • 国家 JP

  • 入库时间 2022-08-21 18:20:01

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