Low-latency power-dividing clocking scheme for adiabatic quantum-flux-parametron logic

摘要

Adiabatic quantum-flux-parametron (AQFP) logic is a highly energy-efficient superconductor logic family. Traditionally, AQFP circuits have relied on the four-phase clocking scheme, which uses a pair of ac current sources with a 90° phase difference. The operation of each logic gate thus takes a quarter clock cycle, leading to a relatively long latency for some applications. In this Letter, we propose a low-latency clocking scheme for AQFP logic based on microwave power dividers (PDs). The whole circuit is powered by a single excitation current, which is equally split for each logic stage by a serial-type PD. As a result, the latency between adjacent logic stages is determined by the transmission line length (propagation delay) inside the PD, which can be much shorter than a quarter clock cycle. Note that the low-latency performance is independent of the horizontal length of the AQFP circuit, and thus, the proposed clocking scheme is applicable to large-scale designs where a large number of gates are horizontally placed in a single stage. For validation, several numerical simulations are conducted and a six-stage AQFP test circuit is demonstrated using the proposed power-dividing clocking scheme (with a designed latency of 20 ps per gate) at a temperature of 4.2 K.