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An improved methodology for extracting interface state density at Si_3N_4/CaN

机译:一种在Si_3N_4 / CaN下提取界面态密度的改进方法

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In this Letter, a series of metal-insulator-semiconductor capacitors consisting of Si3N4 dielectrics with different thicknesses on GaN have been fabricated to investigate their interface states. The measurement value extracted from ultraviolet assisted capacitance-voltage methods can be explained by the existence of spatially uniform hole traps in Si3N4. An improved model combining the effects from interface states and hole traps in Si3N4 is proposed to extract the interface state density (D-it) accurately. Based on the model, D-it can be obtained by extrapolating the trap density to a zero-thickness dielectric. The extracted average D-it value of the Si3N4/GaN interface is similar to 3.8 x 10(11) cm(-2) eV(-1), and the hole trap concentration in Si3N4 is similar to 3.1 x 10(18) cm(-3). The results, model, and analysis presented here provide new insights into studying D-it of various dielectrics on GaN and other wide-bandgap semiconductors. Published under license by AIP Publishing.
机译:在这封信中,制造了一系列由GaN上不同厚度的Si3N4电介质组成的金属绝缘体半导体电容器,以研究其界面状态。 Si3N4中存在空间均匀的空穴陷阱,可以解释从紫外线辅助电容电压法提取的测量值。提出了一种结合Si 3 N 4中界面态和空穴陷阱的影响的改进模型,以准确地提取界面态密度(D-it)。根据该模型,可以通过将陷阱密度外推至零厚度电介质来获得D-it。 Si3N4 / GaN界面的提取平均D-it值类似于3.8 x 10(11)cm(-2)eV(-1),Si3N4中的空穴陷阱浓度类似于3.1 x 10(18)cm (-3)。本文介绍的结果,模型和分析为研究GaN和其他宽带隙半导体上各种电介质的D-it提供了新的见识。由AIP Publishing授权发布。

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