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Increased Schottky barrier heights for Au on n- and p-type GaN using cryogenic metal deposition

机译:使用低温金属沉积技术增加n和p型GaN上Au的肖特基势垒高度

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摘要

An enhancement of ~ 0.18 eV (an 18% increase) in Schottky barrier height was obtained for Au deposited at cryogenic temperatures on n-type GaN relative to conventional deposition at 300 K (barrier height of 1.0 eV). Enhancements of 0.04-0.11 eV were achieved for Au deposition on p-GaN under the same conditions. The increase in barrier height on n-GaN persists for annealing temperatures up to ~ 200 ℃. At higher annealing temperatures, both types of diodes show a deterioration in rectifying behavior. The reverse current of low temperature deposited diodes was approximately two orders of magnitude lower than conventional Au-GaN diodes. The ideality factor of the cryogenically processed n-type devices (~ 1.06) was similar to that for room temperature diodes (1.13). This simple process method has potential for improving output resistance and power gain and lowering gate leakage current and noise in GaN-based transistors.
机译:与在300 K(1.0 eV的势垒高度)下的常规沉积相比,在低温下在n型GaN上沉积的Au的肖特基势垒高度提高了〜0.18 eV(增加了18%)。在相同条件下,p-GaN上的Au沉积可提高0.04-0.11 eV。在高达200℃的退火温度下,n-GaN上势垒高度的增加持续存在。在较高的退火温度下,两种类型的二极管都表现出整流性能的下降。低温沉积二极管的反向电流比传统的Au / n-GaN二极管低大约两个数量级。经过低温处理的n型器件的理想因子(〜1.06)与室温二极管的理想因子(1.13)相似。这种简单的工艺方法具有改善GaN基晶体管的输出电阻和功率增益,降低栅极泄漏电流和噪声的潜力。

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