A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps precision in 0.35 μm CMOS

摘要

This paper presents a clock generator circuit for a high-speed analog-to-digital converter (ADC). A time-interleaved ADC requires accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at a speed of 166 MS/s, which corresponds to an equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 μm SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies a 0.6 mm2 silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted using 1 ps precision.