A new hybrid phase detector for reduced lock time and timing jitter of phase-locked loops

摘要

This paper presents a new hybrid phase detector called hybrid phase detector that possesses the characteristics of two-XOR linear phase detectors and improved bang–bang binary phase detectors. Phase-locked loops (PLLs) with the proposed hybrid phase detector possess the intrinsic advantage of the low timing jitter of PLLs with a two-XOR phase detector in lock states and the fast locking process of PLLs with an improved bang–bang phase detector. The effectiveness of the proposed phase detector is quantified by comparing the performance of three PLLs with identical loop components except phase detectors implemented in UMC-0.13 μm 1.2 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3V3 devices models that account for both the parasitics and high-order effects of devices. Simulation results demonstrate that PLLs with the hybrid phase detector has the same lock time as that of the PLL with an improved bang–bang phase detector. The amplitude of the fluctuation of the control voltage of the PLL with the hybrid phase detector is the same as that of the PLL with an improved bang–bang phase detector in the transient region and the same as that of the PLL with a two-XOR phase detector when the lock state is established. The timing jitter of the PLL with the hybrid phase detector is the same as that of the PLL with the two-XOR phase detector in the lock state and is much lower as compared with that of the PLL with the improved bang–bang phase detector.