8 mW 1.65-Gbps continuous-time equalizer with clock attenuation detection for digital display interface

摘要

This paper presents a continuous-time equalizer which provides a low-power, small area and low-cost solution for a DDI implementation. Proposed equalizer adopts clock attenuation detector, enabling one to eliminate complex-and-large feed-back loops, and to achieve compact design and low-power consumption. Using the attenuation signal to all four adaptive equalizer filters composed of three signal channels and a clock channel, one curtails three adaptive attenuation detectors in a multi-channel DDI. The design was done in 0.18-μm CMOS technology. Experimental results summarize that this equalizer can compensate up to −33 dB channel attenuation at 1.65-Gbps DDI rate, showing eye-width of 0.70 UI. Its average power consumption is 8 mW and the effective area is 0.127 mm2. This power consumption is very low in comparison to those of previous researches and the effective area is very small.