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Low phase-noise VCO utilizing modified symmetric load and partial positive feedback for FDSM

机译:利用修正对称负载和部分正反馈的FDSM的低相位噪声VCO

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The voltage-controlled oscillator (VCO) in frequency-based UpdeltaUpsigmaUpdeltaUpsigma modulator (FDSM) systems behaves as a voltage-to-phase integrator converting an analog input voltage to phase information. Tuning range and phase noise are the most important factors of the basic design of a VCO in FDSM systems. In this paper a novel low phase-noise and wide tuning-range differential VCO based on a differential ring oscillator with modified symmetric load and a partial positive feedback in the differential delay cell is presented. The VCO is combined with a new bias circuit and implemented using 90 nm CMOS process technology. By using modified NMOS symmetric loads and a PMOS tail for delay cells, the VCO phase noise can be reduced with more than 13 dB compared to that of the conventional approach, achieving −125 dBc/Hz at 500 kHz offset from the center frequency of 450 MHz. The wide tuning-range by using two added transistors (parallel with the active loads) increases the operating frequency range by about 22%, while the partial positive feedback provides the necessary bias condition for the circuit to oscillate. The designed VCO operating at a low power supply voltage of 0.6V can achieve low power consumption of 670 μW at oscillation frequency of 800 MHz and good linearity reducing harmonic distortion in the UpdeltaUpsigmaUpdeltaUpsigma modulator.
机译:基于频率的UpdeltaUpsigmaUpdeltaUpsigma调制器(FDSM)系统中的压控振荡器(VCO)充当将模拟输入电压转换为相位信息的电压相位积分器。调谐范围和相位噪声是FDSM系统中VCO基本设计的最重要因素。本文提出了一种新型的低相位噪声和宽调谐范围的差分VCO,该差分VCO基于差分环形振荡器,具有经修改的对称负载和差分延迟单元中的部分正反馈。 VCO与新的偏置电路相结合,并使用90 nm CMOS工艺技术实现。通过将改进的NMOS对称负载和PMOS尾部用于延迟单元,与传统方法相比,可以将VCO相位噪声降低13 dB以上,在从450的中心频率偏移500 kHz时达到−125 dBc / Hz兆赫通过使用两个附加的晶体管(与有源负载并联)来实现宽调谐范围,可使工作频率范围增加约22%,而部分正反馈则为电路振荡提供了必要的偏置条件。设计的VCO在0.6V的低电源电压下工作,可以在800 MHz的振荡频率下实现670μW的低功耗,并具有良好的线性度,从而降低了UpdeltaUpsigmaUpdeltaUpsigma调制器中的谐波失真。

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