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MEG: A RISCV-based System Emulation Infrastructure for Near-data Processing Using FPGAs and High-bandwidth Memory

机译:MEG:基于RISC的系统仿真基础设施,用于使用FPGA和高带宽内存的近数据处理

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Emerging three-dimensional (3D) memory technologies, such as the Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM), provide high-bandwidth and massive memory-level parallelism. With the growing heterogeneity and complexity of computer systems (CPU cores and accelerators, etc.), efficiently integrating emerging memories into existing systems poses new challenges and requires detailed evaluation in a realistic computing environment. In this article, we propose MEG, an open source, configurable, cycle-exact, and RISC-V-based full-system emulation infrastructure using FPGA and HBM. MEG provides a highly modular hardware design and includes a bootable Linux image for a realistic software flow, so that users can perform cross-layer software-hardware co-optimization in a full-system environment. To improve the observability and debuggability of the system, MEG also provides a flexible performance monitoring scheme to guide the performance optimization. The proposed MEG infrastructure can potentially benefit broad communities across computer architecture, system software, and application software. Leveraging MEG, we present two cross-layer system optimizations as illustrative cases to demonstrate the usability of MEG. In the first case study, we present a reconfigurable memory controller to improve the address mapping of standard memory controller. This reconfigurable memory controller along with its OS support allows us to optimize the address mapping scheme to fully exploit the massive parallelism provided by the emerging three-dimensional (3D) memories. In the second case study, we present a lightweight IOMMU design to tackle the unique challenges brought by 3D memory in providing virtual memory support for near-memory accelerators. We provide a prototype implementation of MEG on a Xilinx VU37P FPGA and demonstrate its capability, fidelity, and flexibility on real-world benchmark applications. We hope MEG fills a gap in the space of publicly available FPGA-based full-system emulation infrastructures, specifically targeting memory systems, and inspires further collaborative software/hardware innovations.
机译:新兴的三维(3D)内存技术,例如混合存储器立方体(HMC)和高带宽存储器(HBM),提供高带宽和大规模的内存级并行性。随着计算机系统的不断增长的异质性和复杂性(CPU核心和加速器等),有效地将新兴的存储器集成到现有系统中造成新的挑战,并且需要在现实计算环境中进行详细的评估。在本文中,我们使用FPGA和HBM提出了MEG,开源,可配置,周期精确和RISC-V的全系统仿真基础架构。 MEG提供高度模块化的硬件设计,包括可启动的Linux图像,用于逼真的软件流,因此用户可以在全系统环境中执行跨层软件 - 硬件协同优化。为了提高系统的可观察性和调试性,MEG还提供灵活的性能监测方案来指导性能优化。所提出的MEG基础设施可能会使计算机架构,系统软件和应用软件中的广泛社区受益。利用MEG,我们展示了两个跨层系统优化作为说明性情况,以证明MEG的可用性。在第一种案例研究中,我们介绍了一个可重构的存储器控​​制器,以改善标准存储器控制器的地址映射。该可重新配置的存储器控​​制器以及其OS支持允许我们优化地址映射方案以充分利用由新出现的三维(3D)存储器提供的大规模并行性。在第二个案例研究中,我们提出了一种轻量级的IOMMU设计,以解决3D内存所带来的独特挑战,在为近存储器加速器提供虚拟内存支持时。我们在Xilinx VU37P FPGA上提供MEG的原型实施,并展示了其对现实世界基准应用的能力,保真度和灵活性。我们希望MEG填补公开的基于FPGA的全系统仿真基础设施的空间差距,专门针对内存系统,并激发进一步的协作软件/硬件创新。

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